Constraints on the Use of Boundary-Scan for Fault Injection



The Boundary-Scan technology was proposed fifteen years
ago to overcome the limitations of testing digital devices due to the
increasing complexity and greater miniaturization of integrated circuits
and boards. The use of pin-level fault-injection faced similar difficulties
and became obsolete for that reason. In this paper we discuss the use
of the Boundary-Scan infrastructure for fault-injection purposes. Several
fundamental constraints of such approach are identified. Generic digital
systems and processors with Boundary-Scan based On-Chip Debugging
(OCD) are considered as target system candidates. We observe that by
combining OCD mechanisms with modified boundary-scan cells most of
the constraints reported are solved. Finally, some key properties of the
technology such as the orthogonality to the purely functional architecture
and the low abstraction level access as well as the standard interface and
description language provided make it a good candidate to provide a
standardized flexible fault injection framework.


Boundary-scan, fault-injection, IEEE 1149.1


Fault Injection


First Latin-American Symposium on Dependable Computing, LADC 2003, October 2003

Cited by

Year 2005 : 1 citations

 On-chip Debugging-based Fault Emulation for Robustness Evaluation of Embedded Software Components, J Pardo, JC Ruiz, JC Campelo, P Gil, PRDC 2005, Changsha, Hunan, China, Dec. 12-14, 2005