CISUC

Evaluating Xilinx SEU Controller Macro for Fault Injection

Authors

Abstract

This paper presents a preliminary evaluation of the SEU Controller Macro, a VHDL component developed by Xilinx for the detection and recovery of single event upsets, as a
building block of an FPGA fault-injector. We found that this SEU Controller Macro is extremely effective for injecting faults into the FPGA configuration memory, as single and double bitflips, with precise location, virtually no intrusiveness, and coarse timing accuracy. We present some clues on how to extend its functionalities to build a fully-fledge FPGA fault injector.

Keywords

fault injection, FPGA, SEU, embedded systems

Subject

FPGA fault injection

Conference

The 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2013), June 2013

PDF File


Cited by

Year 2018 : 2 citations

 B. Shen, L. Peng and Y. Xie, "Reliability enhanced data processing system capable of runtime fault recovery," 2018 IEEE 3rd International Conference on Big Data Analysis (ICBDA), Shanghai, 2018, pp. 122-127.
doi: 10.1109/ICBDA.2018.8367662

 M. Darvishi, Y. Audet and Y. Blaquière, "Delay Monitor Circuit and Delay Change Measurement Due to SEU in SRAM-Based FPGA," in IEEE Transactions on Nuclear Science, vol. 65, no. 5, pp. 1153-1160, May 2018.
doi: 10.1109/TNS.2018.2828785

Year 2016 : 1 citations

 Souari, Anis, et al. "Towards an efficient SEU effects emulation on SRAM-based FPGAs." Microelectronics Reliability 66 (2016): 173-182.

Year 2015 : 2 citations

 H Quinn, M Wirthlin, “Validation Techniques for Fault Emulation of SRAM-based FPGAs”, IEEE Transactions on Nuclear Science, 2015

 Hiari, Omar Mohammad. "System-on-chip based diverse redundancy for automotive reliability." PhD diss., Oakland University, 2015.